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Espressif Systems /ESP32-H2 /SPI0 /SPI_SMEM_PMS0_ATTR

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Interpret as SPI_SMEM_PMS0_ATTR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI_SMEM_PMS_RD_ATTR)SPI_SMEM_PMS_RD_ATTR 0 (SPI_SMEM_PMS_WR_ATTR)SPI_SMEM_PMS_WR_ATTR 0 (SPI_SMEM_PMS_ECC)SPI_SMEM_PMS_ECC

Description

SPI1 flash ACE section 0 start address register

Fields

SPI_SMEM_PMS_RD_ATTR

1: SPI1 external RAM ACE section %s read accessible. 0: Not allowed.
SPI_SMEM_PMS_WR_ATTR

1: SPI1 external RAM ACE section %s write accessible. 0: Not allowed.
SPI_SMEM_PMS_ECC

SPI1 external RAM ACE section %s ECC mode, 1: enable ECC mode. 0: Disable it. The external RAM ACE section %s is configured by registers SPI_SMEM_PMS%s_ADDR_REG and SPI_SMEM_PMS%s_SIZE_REG.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data